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C8051F380/1/2/3/4/5/6/7/C
17.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “27.4. Watchdog Timer Mode” on
page 308; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
17.7. Flash Error Reset
If a Flash program read, write, or erase operation targets an illegal address, a system reset is generated.
This may occur due to any of the following:
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Programming hardware attempts to write or erase a Flash location which is above the user code space
address limit.
A Flash read from firmware is attempted above user code space. This occurs when a MOVC operation
is attempted above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
A Flash read, write, or erase attempt is restricted due to a Flash security setting.
A Flash write or erase is attempted when the V DD monitor is not enabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
17.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
17.9. USB Reset
Writing 1 to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as
a reset source, a system reset will be generated when either of the following occur:
1. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be
enabled for RESET signaling to be detected. See Section “21. Universal Serial Bus Controller (USB0)”
on page 172 for information on the USB Function Controller.
2. A falling or rising voltage on the VBUS pin.
The USBRSF bit will read 1 following a USB reset. The state of the RST pin is unaffected by this reset.
Rev. 1.4
133
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